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In this paper we study the trade-offs and benefits of using ILT-based SRAF placement/OPC over conventional SRAF placement/OPC for various front-end and back-end design configurations on a full chip. We explore the use models and benefits of using ILT-based Local Printability Enhancement (LPE) in an automated flow to eliminate hot spots that can be present on the full chip after conventional SRAF placement/OPC. We study the impact on process-window, performance, and mask manufacturability. © (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.