ИСТИНА

This research thesis presents the assessment/determination of level of hazard/threat to emerging microelectronics devices in Low Earth Orbit (LEO) space radiation environment with different orbital parameters to predict the performance of onboard memories and/or random logic devices fabricated in 65nm technology node. In this context, the various parameters for space radiation environment have been analyzed to characterize the ionizing radiation environment effects on proposed VLSI devices. The space radiation environment has been modeled in the form of particles trapped in Van-Allen radiation belts (RBs), Energetic Solar Particles Events (ESPE) and Galactic Cosmic Rays (GCR) whereas its potential effects on Device- Under-Test (DUT) has been predicted in terms of Total Ionizing Dose (TID), Single-Event Effects (SEE) and Displacement Damage Dose (DDD). The required mitigation techniques including necessary shielding requirements to avoid undesirable effects of radiation environment at device level has been determined with assumed typical 100 mils or 2.54 mm thickness of Aluminum shielding. In order to evaluate space radiation environment and analyze energetic particles effects on 6T SRAM bit-cell, OMERE toolkit developed by TRAD was utilized. Therefore, this thesis focuses on the radiation response of six transistors (6T) Static Random Access Memory (SRAM) bit-cell, circuits operating in radiation environment existing at Low Earth Orbit (LEO). The performance of bulk CMOS technology based devices was evaluated by characterizing its susceptibility to Single Event Upsets (SEUs). Further, the impact of technology scaling on SEU rates, Linear Energy Transfer (LET) threshold and area of cross-section per bit/device due to ionizing radiation environment at an altitude up to 1000 km was simulated. Due to irradiation of gate and drain regions of off-state NMOS transistor in SRAM bit cell with LET spectrum transmitted through shielding, the magnitude and pulse duration of generated transient current as well as voltage pulses were analyzed and sensitive strike location for 65 nm SRAM bitcell were presented in SEU map and cumulative upset probability for SEU occurrence was presented as a function of Vdmin i.e. minimum differential voltage between the internal nodes Q, ͞Q of SRAM. The effect of Total Ionizing Dose (TID) on MOS devices in LEO environment to cause electrostatic potential variations was determined. Finally, the SEU sensitive parameters required to predict SEU rate of on-board target device i.e. 65nm SRAM was calculated with typical Aluminum spot shielding using fully physical mechanism simulation. In order to characterize the robustness of scaled CMOS devices, state of the art simulation tools such as Klayout, GDS2MESH, Visual TCAD/Genius, GSEAT/Visual Particle, runSEU were utilized whereas LEO radiation environment assessment, TID estimation and upset rate prediction was accomplished with the help of OMERE-TRAD software.