Аннотация:Equivalence Checking (EC) and functional Engineering Change Order (ECO) are indispensable techniques in modern Very-Large-Scale Integrated circuits (VLSI) design flow. But analyzing an entire design is not always practical for large-scale designs because of their size and complexity. The international contest “2015 CAD Contest at ICCAD” (ICCAD) participants were requested to investigate the problem of partitioning large designs into corresponding smaller designs in order to reduce their equivalence checking and functional correction problems. This paper proposes a three-phase approach to the contest problem solution: a global decomposition phase for original circuits partitioning into smaller ones, a matching phase for corresponding pairs identification and the best pairs selection and a local decomposition phase of the remaining subcircuits using dynamic programming algorithm. Experimental results indicate, that proposed approach is very efficient in practice. It shows improvement for the ECO benchmarks results compared to the results of the prize winning entries of the ICCAD entries and to the results recently published in literature.