ИСТИНА

Following the Moore’s law forces one to constantly decrease the node size of ULSI devices that gives rise to a lot of new challenges in semiconductor production. New interconnect materials with low dielectric permittivity (low-k materials) have to be designed and integrated to solve the problems of interconnect delay, dynamic power consumption and crosstalk [1]. Organosilicate glass layer with ordered porosity (37-40%) and a k-value of 2.2 (OSG 2.2) is one of the candidate for sub 10 nm technology node. Different steps during the integration process can lead to low-k degradation caused by loosing of hydrophobicity, subsequent moisture uptake and increasing of k-value [1,3]. This steps include hardmask deposition, low-k etching, barrier layer deposition, metal filling and chemical mechanical polishing(CMP). 7-10 nm node technology demands integrated k-value to be less than 2.4 and that is why different sources of damage should be examined. To improve selectivity of photoresist etching over the low-k, hardmask is deposited over the dielectric surface. The hardmask is a multilayer stack and it’s first layer is a thin oxide that is used to provide low-k surface sealing and protection during the rest of the hardmask deposition. It was shown by FTIR analysis and ellipsometric porosimetry, that 10nm of the first hardmask layer is enough to reach this goals. The next step of integration is a low-k etching. This step can seriously degrade low-k material [1,3,4] and the etching recipe screening and hardmask modifications are demanded to reduce the etching step damage. Except of the low damage, etching recipe should provide smooth structure bottom necessary for appropriate quality of metal barrier deposition. High roughness of low-k surface after the etching can lead to low quality of barrier deposition and subsequent barrier and Cu penetration into the low-k, that seriously deteriorates dielectric properties by increasing leakage current and decreasing breakdown voltage. Two etching recipes were chosen to etch the low-k layer and TEM analysis was performed on integrated structures to reveal quality of metallization step. The TEM results were compared with AFM data of surface roughness measurements and improvement of barrier deposition by decreasing of surface roughness after the etching was proved. CMP was the last step of integration under the consideration[1,2]. Alkaline slurries that are usually used for CMP can lead to loosing of material hydrophobicity and k-value increasing. Wafers coated with low-k layer with and without sealing layer experienced CMP process. FTIR data and k-value C-V measurements showed CMP process modify only the thin top layer of low-k, which can be restored then by thermal annealing. Among the all integration steps considered in this study, etching step appears to be the most damageable one and specifically vacuum ultraviolet (VUV) photons bring most of the damage during the etching [4]. Experiments with different hardmasks showed that 30nm of the oxide sealing layer or 50nm of amorphous carbon can reduce VUV damage in case of Ar plasma, while Ar is used as a carrier gas in etching recipes. The recipe for low-k etching should provide a tradeoff between VUV light intensity reduction, high etch rate needed for radical damage excluding and a low surface roughness. 1. Mikhail R. Baklanov, Paul S. Ho, Ehrenfried Zschech. Advanced interconnects for ULSI technology, John Willey and Sons, Chichester, 2012. 2. Parshuram B. Zantye, Ashok Kumar, A.K. Sikder. “Chemical mechanical planarization for microelectronics applications” Materials Science and Engineering R 45 (2004) 89–220 3. R. J. O. M. Hoofman, G. J. A. M. Verheijden et al. "Challenges in the implementation of low-k dielectrics in the back-end of line". Microelectronic Engineering, 80, 337 (2005). 4. A. Zotovich, M. Krishtab, F. Lazzarino, M.R. Baklanov. “The chemistry screening for ultra low-k dielectrics room temperature plasma etching”. ICMNE-2014